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  rev. 1.4 november 2010 www.aosmd.com page 1 of 18 aoz1242 ezbuck? 3a simple buck regulator general description the aoz1242 is a high efficiency, simple to use, 3a buck regulator flexible enough to be optimized for a variety of applications. the aoz1242 works from a 4.5v to 32v input voltage range, and provi des up to 3a of continuous output current on each buck regulator output. the output voltage is adjustable down to 0.8v. the aoz1242 comes in an so-8 or dfn-8 package and is rated over a -40c to +85c ambient temperature range features 4.5v to 32v operating input voltage range 70m ? internal nfet, efficiency: up to 95% internal soft start output voltage adjustable down to 0.8v 3a continuous output current fixed 370khz pwm operation cycle-by-cycle current limit short-circuit protection thermal shutdown small size, so-8 or dfn-8 package applications point of load dc/dc conversion set top boxes dvd drives and hdd lcd monitors & tvs cable modems telecom/networking/datacom equipment typical application figure 1. 3.3v/3a buck regulator lx vin bs vin vout fb gnd en vbias comp c1 22f c7 c4 c2, c3 22f x 2 r1 r2 r c c c l1 6.8h aoz1242
aoz1242 rev. 1.4 november 2010 www.aosmd.com page 2 of 18 ordering information aos green products use reduced levels of halogens, and are also rohs compliant. please visit www.aosmd.com/web/qualit y/rohs_compliant.jsp for additional information. pin configuration pin description part number ambient temperature range package environmental AOZ1242AI -40c to +85c so-8 green product aoz1242di -40c to +85c dfn-8 green product vbias vin en comp 1 2 3 4 lx bst gnd fb so-8 (top view) dfn-8 (top thru view) 8 7 6 5 vbias vin en comp 1 2 3 4 lx bst gnd fb 8 7 6 5 vin gnd pin number pin name pin function 1 lx pwm output connection to inductor. lx pin needs to be connected externally. thermal connection for output stage. 2 bst bootstrap voltage input. high side driver s upply. connected to 0.1f capacitor between bst and lx. 3 gnd ground. 4 fb feedback input. it is regulated to 0.8v. the fb pin is used to determine the pwm output voltage via a resistor divider between the output and gnd. 5 comp external loop compensation. output of internal error amplifier. connect a series rc network to gnd for control l oop compensation. 6 en enable pin. the enable pin is active high. connect en pin to v in if not used. do not leave the en pin floating. 7v in supply voltage input. range from 4.5v to 32v. when v in rises above the uvlo threshold the device starts up. all v in pins need to be connected externally. 8 vbias compensation pin of internal linear regulator. place a 1f capacitor between this pin and ground.
aoz1242 rev. 1.4 november 2010 www.aosmd.com page 3 of 18 block diagram absolute maximum ratings exceeding the absolute maximum ratings may damage the device. note: 1. devices are inherently esd s ensitive, handling precautions are required. human body model rating: 1.5k ? in series with 100pf. recommended operating conditions the device is not guaranteed to operate beyond the recommended operating conditions. note: 2. the value of ja is measured with the device mounted on 1-in 2 fr-4 board with 2oz. copper, in a still air environment with t a = 25c. the value in any given applic ation depends on the user's spe- cific board design. 370khz / 24khz oscillator gnd vin en vbias fb comp lx bst otp ilimit pwm control logic 5v ldo regulator uvlo & por +5v gm = 200 a / v softstart reference & bias 0.8v q1 q2 pwm comp isen eamp 0.2v + ? + ? + ? + ? + frequency foldback comparator parameter rating supply voltage (v in ) 34v lx to gnd -0.7v to v in +0.3v en to gnd -0.3v to v in +0.3v fb to gnd -0.3v to 6v comp to gnd -0.3v to 6v bst to gnd v lx +6v vbias to gnd -0.3v to 6v junction temperature (t j ) +150c storage temperature (t s ) -65c to +150c esd rating (1) 2kv parameter rating supply voltage (v in ) 4.5v to 32v output voltage range 0.8v to v in ambient temperature (t a ) -40c to +85c package thermal resistance ( ja ) (2 ) so-8 dfn-8 105c/w 53c/w
aoz1242 rev. 1.4 november 2010 www.aosmd.com page 4 of 18 electrical characteristics t a = 25c, v in = v en = 12v, unless otherwise specified (3 ) note: 3. specification in bold indicate an ambient temperature range of -40c to +85c. these specifications are guaranteed by design. symbol parameter conditions min. typ. max. units v in supply voltage 4.5 32 v v uvlo input under-voltage lockout threshold v in rising v in falling 4.3 4.1 v i in supply current (quiescent) i out = 0, v fb = 1.2v, v en > 2v 23 ma i off shutdown supply current v en = 0v 320 a v fb feedback voltage 0.782 0.8 0.818 v load regulation 0.5 % line regulation 0.08 % / v i fb feedback voltage input current 200 na enable v en en input threshold off threshold on threshold 2.5 0.6 v v hys en input hysteresis 200 mv modulator f o frequency 315 370 425 khz d max maximum duty cycle 85 % d min minimum duty cycle 6% g vea error amplifier voltage gain 500 v / v g ea error amplifier transconductance 200 a / v protection i lim current limit 3.5 5.5 a over-temperature shutdown limit t j rising t j falling 145 100 c f sc short circuit hiccup frequency v fb = 0v 24 khz t ss soft start interval 4ms pwm output stage r ds(on) high-side switch on-resistance 70 100 m ? high-side switch leakage v en = 0v, v lx = 0v 10 a
aoz1242 rev. 1.4 november 2010 www.aosmd.com page 5 of 18 typical performance characteristics circuit of figure 1. t a = 25c, v in = v en = 24v, v out = 3.3v unless otherwise specified. light load (dcm) operation full load (ccm) operation startup to full load short circuit protection 50% to 100% load transient short circuit recovery 1 s/div 1 s/div 2ms/div 200 s/div 200
aoz1242 rev. 1.4 november 2010 www.aosmd.com page 6 of 18 efficiency curves efficiency v in = 5v 75 80 85 90 95 1.8v output 5.0v output 5.0v output 3.3v output 3.3v output 8.0v output 8.0v output 3.3v output 100 0 0.5 1.0 1.5 2.0 2.5 3.0 current (a) 0 0.5 1.0 1.5 2.0 2.5 3.0 current (a) efficieny (%) efficiency v in = 12v 75 80 85 90 95 100 efficieny (%) efficiency v in = 24v 75 80 85 90 95 100 efficieny (%) 0 0.5 1.0 1.5 2.0 2.5 3.0 current (a)
aoz1242 rev. 1.4 november 2010 www.aosmd.com page 7 of 18 detailed description the aoz1242 is a current-mode step down regulator with integrated high side nmos switch. it operates from a 4.5v to 32v input voltage range and supplies up to 3a of load current. the duty cycle can be adjusted from 6% to 85% allowing a wide range of output voltage. features include enable control, power-on reset, input under voltage lockout, fixed internal soft-start and thermal shut down. the aoz1242 is available in so-8 or dfn-8 package. enable and soft start the aoz1242 has internal soft start feature to limit in-rush current and ensure the output voltage ramps up smoothly to regulation voltage. a soft start process begins when the input voltage rises to 4.1v and voltage on en pin is high. in soft start process, the output voltage is ramped to regulation voltage in typically 6.8ms. the 6.8ms soft start time is set internally. connect the en pin to v in if enable function is not used. pull it to ground will disable th e aoz1242. do not leave it open. the voltage on en pin must be above 2.5 v to enable the aoz1242. when voltage on en pin falls below 0.6v, the aoz1242 is disabled. if an application circuit requires the aoz1242 to be disabled, an open drain or open collector circuit should be used to interface to en pin. steady-state operation under steady-state conditions, the converter operates in fixed frequency and continuous-conduction mode (ccm). the aoz1242 integrates an internal n-mosfet as the high-side switch. inductor current is sensed by amplifying the voltage drop across the drain to source of the high side power mosfet. since the n-mosfet requires a gate voltage higher than the input voltage, a boost capacitor connected between lx pin and bst pin drives the gate. the boost capacitor is charged while lx is low. an internal 10 ? switch from lx to gn d is used to insure that lx is pulled to gnd even in the light load. output voltage is divided down by the external voltage divider at the fb pin. the difference of the fb pin voltage and reference is amplified by the internal transconductance error amplifier. the error voltage, which shows on the comp pin, is compared against the current signal, which is sum of inductor current signal and ramp compensation signal, at pwm comparator inpu t. if the current signal is less than the error voltage, the internal high-side switch is on. the inductor current flows from the input through the inductor to the output. when the current signal exceeds the error voltage, the high-side switch is off. the inductor current is freewheeling through the schottky diode to output. switching frequency the aoz1242 switching frequency is fixed and set by an internal oscillator. the switching freque ncy is set 370khz. output voltage programming output voltage can be set by feeding back the output to the fb pin with a resistor divider network. in the application circuit shown in fi gure 1. the resistor divider network includes r 1 and r 2 . usually, a design is started by picking a fixed r 2 value and calculating the required r2 with equation below. some standard values for r 1 and r 2 for the most commonly used output voltages are listed in table 1. table 1. the combination of r 1 and r 2 should be large enough to avoid drawing excessive current from the output, which will cause power loss. protection features the aoz1242 has multiple prot ection features to prevent system circuit damage under abnormal conditions. over current protection (ocp) the sensed inductor current signal is also used for over current protection. since the aoz1242 employs peak current mode control, the comp pin voltage is proportional to the peak inductor current. the comp pin voltage is limited to be between 0.4v and 2.5v internally. the peak inductor current is automatically limited cycle-by-cycle. the cycle-by-cycle current limit threshold is internally set. when the load current reaches the current limit threshold, the cycle by cycle current limit circuit turns off the high side switch immediately to terminate the current duty cycle. the indu ctor current stop rising. the cycle-by-cycle current limit protection directly limits inductor peak current. the average inductor current is also limited due to the limitation on peak inductor current. v o (v) r 1 (k ? ) r 2 (k ? ) 0.8 1.0 open 1.2 4.99 10 1.5 10 11.5 1.8 12.7 10.2 2.5 21.5 10 3.3 31.6 10 5.0 52.3 10 v o 0.8 1 r 1 r 2 ------ - + ?? ?? ?? =
aoz1242 rev. 1.4 november 2010 www.aosmd.com page 8 of 18 when cycle by cycle current lim it circuit is triggered, the output voltage drops as the duty cycle decreasing. the aoz1242 has internal short circuit protection to pro- tect itself from ca tastrophic failure un der output short cir- cuit conditions. the fb pin voltage is proportional to the output voltage. whenever fb pin voltage is below 0.2v, the short circuit protection circuit is triggered. to prevent current limit running away, when comp pin voltage is higher than 2.1 v, the short circ uit protection is also trig- gered. as a result, the conv erter is shut down and hic- cups at a frequency equals to 1/16 of normal switching frequency. the conver ter will start up via a soft start once the short circuit condition disappears. in short circuit pro- tection mode, the inductor average current is greatly reduced because of the low hiccup frequency. power-on reset (por) a power-on reset circuit monitors the input voltage. when the input voltage exceeds 4.3v, the converter starts operation. when input voltage falls below 4.1v, the converter will stop switching. thermal protection an internal temperature sensor monitors the junction temperature. it shuts down the internal control circuit and high side nmos if the junction temperature exceeds 145c. the regulator will rest art automatically under the control of soft-start circuit when the junction temperature decreases to 100c. application information the basic aoz1242 application circuit is shown in figure 1. component selection is explained below. input capacitor the input capacitor (c 1 in figure 1) must be connected to the v in pin and gnd pin of the aoz1242 to maintain steady input voltage and filter out the pulsing input current. the voltage rating of input capacitor must be greater than maximum input vo ltage plus ripple voltage. the input ripple voltage can be approximated by equa- tion below: since the input current is discontinuous in a buck converter, the current stress on the input capacitor is another concern when selecting the capacitor. for a buck circuit, the rms value of i nput capacitor current can be calculated by: if let m equal the conversion ratio: the relationship between the input capacitor rms current and voltage conversion ratio is calculated and shown in figure 2. it can be seen that when v o is half of v in , c in is under the worst cu rrent stress. the worst current stress on cin is 0.5 x i o . figure 2. i cin vs. voltage conversion ratio for reliable operation and best performance, the input capacitors must have current rating higher than i cin_rms at worst operating conditions. ceramic capacitors are preferred for input capacitors because of their low esr and high ripple current rating. depending on the application circuits, other low esr tantalum capacitor or aluminum electrolytic ca pacitor may also be used. when selecting ceramic capacitors, x5r or x7r type dielectric ceramic capacitors are preferred for their better temperature and voltage characteristics. note that the ripple current rating from capacitor manufactures is based on certain amount of life time. further de-rating may be necessary for practical design requirement. inductor the inductor is used to suppl y constant current to output when it is driven by a swit ching voltage. for given input and output voltage, inductance and switching frequency together decide the inductor ripple current, which is, the peak inductor current is: high inductance gives low indu ctor ripple current but requires larger size inductor to avoid saturation. low ripple current reduces induct or core losses. it also v in i o fc in ----------------- 1 v o v in -------- - ? ?? ?? ?? v o v in -------- - = i cin_rms i o v o v in -------- - 1 v o v in -------- - ? ?? ?? ?? = v o v in -------- - m = 0 0.1 0.2 0.3 0.4 0.5 0 0.5 1 m i cin_rms (m) i o i l v o fl ---------- - 1 v o v in -------- - ? ?? ?? ?? = i lpeak i o i l 2 -------- + =
aoz1242 rev. 1.4 november 2010 www.aosmd.com page 9 of 18 reduces rms current through inductor and switches, which results in less conduction loss. when selecting the inductor, make sure it is able to handle the peak current without saturation even at the highest operating temperature. the inductor takes the highest current in a buck circuit. the conduction loss on inductor needs to be checked for thermal and efficiency requirements. surface mount inductors in different shape and styles are available from coilcraft, elytone and murata. shielded inductors are small and radiate less emi noise, but they cost more than unshielded inductors. the choice depends on emi requirement, price and size. output capacitor the output capacitor is selected based on the dc output voltage rating, output ripple voltage specification and ripple current rating. the selected output capacitor must have a higher rated voltage specification than the maximum desired output voltage including ripple. de-rating needs to be consid- ered for long term reliability. output ripple voltage specif ication is another important factor for selecting the outp ut capacitor. in a buck con- verter circuit, output ripple voltage is determined by inductor value, switching frequency, output capacitor value and esr. it can be calculated by the equation below: where; c o is output capacitor value and esr co is the equivalent series resistor of output capacitor. when low esr ceramic capacitor is used as output capacitor, the impedance of the capacitor at the switch- ing frequency dominates. output ripple is mainly caused by capacitor value and inductor ripple current. the output ripple voltage calculation can be simplified to: if the impedance of esr at switching frequency dominates, the output ripple voltage is mainly decided by capacitor esr and inductor ripple current. the output ripple voltage calculation can be further simplified to: for lower output ripple voltage across the entire operating temperature range, x5r or x7r dielectric type of ceramic, or other low esr tantalum capacitor or aluminum electrolytic capa citor may also be used as output capacitors. in a buck converter, output c apacitor current is continuous. the rms current of output capacitor is decided by the peak to peak inductor ripple current. it can be calculated by: usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. when the buck inductor is selected to be very small and inductor ripple current is hi gh, output capacitor could be overstressed. schottky diode selection the external freewheeling diode supplies the current to the inductor when the high side nmos switch is off. to reduce the losses due to the forward voltage drop and recovery of diode, schottky diode is recommended to use. the maximum reverse voltage rating of the chosen schottky diode should be greater than the maximum input voltage, and the current rating should be greater than the maximum load current. loop compensation the aoz1242 employs peak current mode control for easy use and fast transient response. peak current mode control eliminates the double pole effect of the output l&c filter. it greatly simplif ies the compensation loop design. with peak current mode control, the buck power stage can be simplified to be a one-pole and one-zero system in frequency domain. the pole is dominant pole and can be calculated by: the zero is a esr zero due to output capacitor and its esr. it is can be calculated by: where; c o is the output filter capacitor, r l is load resistor value, and esr co is the equivalent series resi stance of output capacitor. v o i l esr co 1 8 fc o ------------------------- + ?? ?? = v o i l 1 8 fc o ------------------------- = v o i l esr co = i co_rms i l 12 ---------- = f p 1 1 2 c o r l ---------------------------------- - = f z 1 1 2 c o esr co ------------------------------------------------ =
aoz1242 rev. 1.4 november 2010 www.aosmd.com page 10 of 18 the compensation design is actually to shape the converter close loop transfer function to get desired gain and phase. several different types of compensation network can be used for ao z1242. for most cases, a series capacitor and resistor network connected to the comp pin sets the pole-zero and is adequate for a stable high-bandwidth control loop. in the aoz1242, fb pin and comp pin are the inverting input and the output of internal transconductance error amplifier. a series r and c compensation network connected to comp provides one pole and one zero. the pole is: where; g ea is the error amplifier transco nductance, which is 200 x 10 -6 a/v, g vea is the error amplifier voltage, and c c is the compensation capacitor the zero given by the external compensation network, capacitor c c (c 5 in figure 1) and resistor r c (r 1 in figure 1), is located at: to design the compensation circuit, a target crossover frequency f c for close loop must be selected. the system crossover frequency is where control loop has unity gain. the crossover frequency is also called the converter bandwidth. generally a higher bandwidth means faster response to load transient. however, the bandwidth should not be too high due to system stability concern. when designing the compensation loop, converter stabil- ity under all line and load condition must be considered. usually, it is recommended to set the bandwidth to be less than 1/10 of switching frequency. it is recommended to choose a crossover frequency less than 30khz. the strategy for choosing r c and c c is to set the cross over frequency with r c and set the compensator zero with c c . using selected cr ossover frequency, f c , to calculate r c : where; f c is desired crossover frequency, v fb is 0.8v, g ea is the error amplifier tran sconductance, which is 200x10 -6 a/v, and g cs is the current sense circuit transconductance, which is 5.64 a/v the compensation capacitor c c and resistor r c together make a zero. this zero is put somewhere close to the dominate pole f p1 but lower than 1/5 of selected crossover frequency. c c can is selected by: the equation above can also be simplified to: an easy-to-use application software which helps to design and simulate the compensation loop can be found at www.aosmd.com . thermal management and layout consideration in the aoz1242 buck regulator circuit, high pulsing cur- rent flows through two circuit loops. the first loop starts from the input capacitors, to the v in pin, to the lx pins, to the filter inductor, to the ou tput capacitor and load, and then return to the input capacitor through ground. current flows in the first loop when t he high side switch is on. the second loop starts from inductor, to the output capacitors and load, to the gnd pin of the aoz1242, to the lx pins of the azo1242. current flows in the second loop when the low side diode is on. in pcb layout, minimizing the two loops area reduces the noise of this circuit and im proves efficiency. a ground plane is recommended to connect input capacitor, output capacitor, and gnd pin of the aoz1242. in the aoz1242 buck regulator circuit, the three major power dissipating components are the aoz1242, exter- nal diode and output inductor . the total power dissipation of converter circuit can be measured by input power minus output power. the power dissipation of in ductor can be approximately calculated by output current and dcr of the inductor. f p 2 g ea 2 c c g vea ------------------------------------------ - = f z 2 1 2 c c r c ----------------------------------- = f c 30 khz = r c f c v o v fb ---------- 2 c o g ea g cs ----------------------------- - = c c 1.5 2 r c f p 1 ---------------------------------- - = c c c o r l r c --------------------- = p total_loss v in i in v o i o ? = p inductor_loss i o 2 r inductor 1.1 =
aoz1242 rev. 1.4 november 2010 www.aosmd.com page 11 of 18 the power dissipation of the diode is: the actual aoz1242 junction temperature can be calculated with power dissipation in the aoz1242 and thermal impedance from junction to ambient. the maximum junction tem perature of aoz1242 is 145c, which limits the maximu m load current capability. the thermal performance of the aoz1242 is strongly affected by the pcb layout. extra care should be taken by users during design process to ensure that the ic will operate under the reco mmended environmental conditions. several layout tips are listed below for the best electric and thermal performance. figure 3a and figure 3b give the example of layout for aoz1242a and aoz1242d respectively. 1. do not use thermal relief connection to the v in and the gnd pin. pour a maximized copper area to the gnd pin and the v in pin to help thermal dissipation. 2. input capacitor should be connected to the v in pin and the gnd pin as close as possible. 3. make the current trace from lx pins to l to co to the gnd as short as possible. 4. pour copper plane on all unused board area and connect it to stable dc nodes, like v in , gnd or v out . 5. keep sensitive signal trace such as trace connected with fb pin and comp pin far away form the lx pins. p diode_loss i o v f 1 v o v in -------- - ? ?? ?? ?? = t junction p total_loss p inductor_loss ? () ja = t ambient ++
aoz1242 rev. 1.4 november 2010 www.aosmd.com page 12 of 18 figure 3a. layout example for AOZ1242AI figure 3b. layout example for aoz1242di r2 c4 cb c1 r1 vin 1 lx bst 2 gnd fb 4 8 vbias 5 6 comp en 3 7 vin gnd l1 vo c2 c 2 rc cc r1 r2
aoz1242 rev. 1.4 november 2010 www.aosmd.com page 13 of 18 package dimensions, so-8 notes: 1. all dimensions are in millimeters. 2. dimensions are inclusive of plating 3. package body sizes exclude mold flash and gate burrs. mold flash at the non-lead sides should be less than 6 mils. 4. dimension l is measured in gauge plane. 5. controlling dimension is millimeter, converted inch dimensions are not necessarily exact. symbols a a1 a2 b c d e1 e e h l dimensions in millimeters min. 1.35 0.10 1.25 0.31 0.17 4.80 3.80 5.80 0.25 0.40 0 d c l h x 45 7 (4x) b 2.20 5.74 0.80 unit: mm 1.27 a1 a2 a 0.1 gauge plane seating plane 0.25 e 8 1 e1 e nom. 1.65 ? 1.50 ? ? 4.90 3.90 1.27 bsc 6.00 ? ? ? max. 1.75 0.25 1.65 0.51 0.25 5.00 4.00 6.20 0.50 1.27 8 symbols a a1 a2 b c d e1 e e h l dimensions in inches min. 0.053 0.004 0.049 0.012 0.007 0.189 0.150 0.228 0.010 0.016 0 nom. 0.065 ? 0.059 ? ? 0.193 0.154 0.050 bsc 0.236 ? ? ? max. 0.069 0.010 0.065 0.020 0.010 0.197 0.157 0.244 0.020 0.050 8
aoz1242 rev. 1.4 november 2010 www.aosmd.com page 14 of 18 tape and reel dimensions, so-8 so-8 carrier tape so-8 reel so-8 tape leader/trailer & orientation tape size 12mm reel size ?330 m ?330.00 0.50 package so-8 (12mm) a0 6.40 0.10 b0 5.20 0.10 k0 2.10 0.10 d0 1.60 0.10 d1 1.50 0.10 e 12.00 0.10 e1 1.75 0.10 e2 5.50 0.10 p0 8.00 0.10 p1 4.00 0.10 p2 2.00 0.10 t 0.25 0.10 n ?97.00 0.10 k0 unit: mm b0 g m w1 s k h n w v r trailer tape 300mm min. or 75 empty pockets components tape orientation in pocket leader tape 500mm min. or 125 empty pockets a0 p1 p2 see note 5 see note 3 see note 3 feeding direction p0 e2 e1 e d0 t d1 w 13.00 0.30 w1 17.40 1.00 h ?13.00 +0.50/-0.20 k 10.60 s 2.00 0.50 g ? r ? v ?
aoz1242 rev. 1.4 november 2010 www.aosmd.com page 15 of 18 package dimensions, 5x4a dfn-8 notes: 1. dimensions and tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. 3. the location of the terminal #1 identifier and terminal numbering convention conforms to jedec publication 95 sp-002. 4. dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. 5. coplanarity applies to the terminals and all other bottom surface metallization. 6. drawing shown are for illustration only. 7. the dimensions with * are just for reference 8. pin #3 and pin #7 are fused to dap. symbols a a3 b d d2 d3 e e2 e l l1 l2 l3 r aaa bbb ccc ddd eee dimensions in millimeters recommended land pattern front view top view bottom view bottom view min. 0.70 0.40 4.90 2.05 1.66 3.90 2.23 0.50 ? nom. 0.75 0.20 ref. 0.45 5.00 2.15 1.76 4.00 2.33 0.95 bsc 0.55 0.40 0.285 ref. 0.835 ref. 0.30 ref. 0.15 0.10 0.10 0.08 0.05 max. 0.80 0.50 5.10 2.25 1.86 4.10 2.43 0.60 ? symbols a a3 b d d2 d3 e e2 e l l1 l2 l3 r aaa bbb ccc ddd eee min. 0.028 0.016 0.190 0.080 0.064 0.154 0.088 0.020 ? nom. 0.30 0.008 ref. 0.018 0.200 0.085 0.070 0.157 0.092 0.037 bsc 0.022 0.016 0.011 ref. 0.033 ref. 0.012 ref. 0.006 0.004 0.004 0.003 0.002 max. 0.032 0.020 0.201 0.089 0.074 0.161 0.096 0.024 ? 4.51 0.285 2.33 1.165 0.285 1.86 0.40 2.25 0.50 typ. 0.95 typ. 0.65 4.20 dimensions in inches b a a3 seating plane d/2 e/2 d e l l2* l3* e2 l2* d3 l1 e d2 chamfer 0.30 pin #1 ida option 1 index area (d/2 x e/2) pin #1 ida option 2 r
aoz1242 rev. 1.4 november 2010 www.aosmd.com page 16 of 18 tape and reel dimensions, 5x4a dfn-8 r0 .40 p0 k0 a0 e e2 d0 e1 d1 b0 package dfn 5x4 (12 mm) a0 b0 k0 e e1 e2 d0 d1 p0 p1 p2 t 5. 3 0 0.10 0.10 4. 3 0 0.10 1.20 min. 1.50 1.50 12.00 0.10 1.75 0.10 5.50 0.10 8 .00 0.20 4.00 0.10 2.00 0.05 0. 3 0 unit: mm t typ. 0.20 feeding direction tape leader/trailer and orientation 0. 3 0 +0.10 / ?0 tr a iler t a pe 3 00mm min. component s t a pe orient a tion in pocket le a der t a pe 500mm min.
aoz1242 rev. 1.4 november 2010 www.aosmd.com page 17 of 18 reel view: c c 0.05 3-1.8 ?96 0.2 6.45 0.05 3-?2. 9 0.05 3-? 1 / 8 " 3-?1 / 4" 8.9 0.1 11.90 14 ref 1.8 5.0 12 ref 41.5 ref 43.00 44.5 0.1 2.00 6.50 10.0 10.71 10 3-?3/1 6 " r48 ref ?86.0 0 .1 2.20 6.2 ?13.00 ?21.20 ?17 . 0 r 1 . 10 r 3 .10 2.00 3.3 4.0 6.10 0.80 3.00 8.00 +0.05 0.00 r 0. 5 1.80 2.5 3 8 44.5 0.1 46.0 0.1 8.0 0.1 40 6 3-?3/16" r 3 .95 6.50 ?90. 0 0 6.0 1.8 1 .8 r1 8.00 0.00 -0.05 n=?100 2 a a a r121 r127 r1 59 r6 r5 5 p b w1 m ii i i 6.0 1 r1 zoom in iii zoom in ii zoom in a tape size 12mm reel size ?330 m ?330 +0.3 -4.0 w1 12.40 +2.0 -0.0 b 2.40 0.3 p 0.5
aoz1242 rev. 1.4 november 2010 www.aosmd.com page 18 of 18 as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. this data sheet contains preliminary data; supplementary data may be published at a later date. alpha & omega semiconductor reserves the right to make changes at any time without notice. life support policy alpha & omega semiconductor products are not author ized for use as critical components in life support devices or systems. part marking AOZ1242AI aoz1242di z1242ai fay part n umbe r assembly lot code fab & assembly location year & w eek code w lt z1242di fay part numbe r assembly lot code fab & assembly location year & week code wlt


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